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74ALVC162334A
16-bit registered driver with inverted register enable and 30 termination resistors (3-state)
Rev. 03 -- 13 December 2006 Product data sheet
1. General description
The 74ALVC162334A is a 16-bit universal bus driver. Data flow is controlled by active LOW output enable (OE), active LOW latch enable (LE), and clock input (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP, the A data is stored in the latch/flip-flop. The 74ALVC162334A is designed with 30 series resistors in both HIGH or LOW output stages. When OE is LOW, the outputs are active. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latch/flip-flop. To ensure the high-impedance state during power-up or power-down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
2. Features
I I I I I I I I I I Wide supply voltage range of 1.2 V to 3.6 V Complies with JEDEC standard 8-1A CMOS low power consumption Direct interface with TTL levels Current drive: 24 mA at 3.0 V MULTIBYTE flow-through standard pinout architecture Low inductance multiple VCC and GND pins for minimum noise and ground bounce Output drive capability 50 transmission lines at 85 C Integrated 30 termination resistors Input diodes to accommodate strong drivers
NXP Semiconductors
74ALVC162334A
16-bit registered driver (3-state)
3. Quick reference data
Table 1. Quick reference data VCC = 3.3 V 0.3 V; GND = 0 V; tr = tf 2.5 ns; CL = 50 pF (see Figure 11). Symbol tPHL Parameter HIGH-to-LOW propagation delay Conditions An to Yn; Figure 5 LE to Yn; Figure 6 CP to Yn; Figure 8 tPLH LOW-to-HIGH propagation delay An to Yn; Figure 5 LE to Yn; Figure 6 CP to Yn; Figure 8 fmax Ci Cio CPD maximum input clock frequency input capacitance input/output capacitance power dissipation capacitance per buffer; VI = GND to VCC transparent mode; output enabled transparent mode; output disabled clocked mode; output enabled clocked mode; output disabled
[1] [2] All typical values are at Tamb = 25 C. CPD is used to determine the dynamic power dissipation (PD) in W. PD = CPD x VCC2 x fi + (CL x VCC2 x fo), where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of outputs.
[2]
Min 1.0 1.3 1.4 1.0 1.3 1.4 150 -
Typ[1] 2.8 2.8 3.2 2.8 2.8 3.2 240 4.0 8.0 10 3 21 15
Max 4.3 4.4 4.9 4.3 4.4 4.9 -
Unit ns ns ns ns ns ns MHz pF pF pF pF pF pF
Figure 8
4. Ordering information
Table 2. Ordering information Temperature range -40 C to +85 C Package Name TSSOP48 Description plastic thin shrink small outline package; 48 leads; body width 6.1 mm Version SOT362-1 Type number 74ALVC162334ADGG
74ALVC162334A_3
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Product data sheet
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74ALVC162334A
16-bit registered driver (3-state)
5. Functional diagram
1 OE 48 CP 25 LE
EN1 2C3 C3 G2 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23
1
1
3D
002aac723
Fig 1. Logic symbol (IEEE/IEC)
OE CP LE A1 D LE CP
Y1
to the 15 other channels
002aac724
Fig 2. Logic diagram
VCC
A1
002aac725
Fig 3. Typical input (data or control)
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Product data sheet
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74ALVC162334A
16-bit registered driver (3-state)
6. Pinning information
6.1 Pinning
OE Y1 Y2 GND Y3 Y4 VCC Y5 Y6
1 2 3 4 5 6 7 8 9
48 CP 47 A1 46 A2 45 GND 44 A3 43 A4 42 VCC 41 A5 40 A6 39 GND 38 A7 37 A8 36 A9 35 A10 34 GND 33 A11 32 A12 31 VCC 30 A13 29 A14 28 GND 27 A15 26 A16 25 LE
002aac722
GND 10 Y7 11 Y8 12 Y9 13 Y10 14 GND 15 Y11 16 Y12 17 VCC 18 Y13 19 Y14 20 GND 21 Y15 22 Y16 23 n.c. 24
74ALVC162334ADGG
Fig 4. Pin configuration for TSSOP48
6.2 Pin description
Table 3. Symbol OE Y1 Y2 GND Y3 Y4 VCC Y5 Y6 Y7 Y8
74ALVC162334A_3
Pin description Pin 1 2 3 4, 10, 15, 21, 28, 34, 39, 45 5 6 7, 18, 31, 42 8 9 11 12 Description output enable input (active LOW) data output 1 data output 2 ground supply (0 V) data output 3 data output 4 positive supply voltage data output 5 data output 6 data output 7 data output 8
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74ALVC162334A
16-bit registered driver (3-state)
Pin description ...continued Pin 13 14 16 17 19 20 22 23 24 25 26 27 29 30 32 33 35 36 37 38 40 41 43 44 46 47 48 Description data output 9 data output 10 data output 11 data output 12 data output 13 data output 14 data output 15 data output 16 not connected latch enable input (active LOW) data input 16 data input 15 data input 14 data input 13 data input 12 data input 11 data input 10 data input 9 data input 8 data input 7 data input 6 data input 5 data input 4 data input 3 data input 2 data input 1 clock input
Table 3. Symbol Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 n.c. LE A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 CP
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74ALVC162334A
16-bit registered driver (3-state)
7. Functional description
Refer to Figure 1 "Logic symbol (IEEE/IEC)" and Figure 2 "Logic diagram".
7.1 Function selection
Table 4. Function selection H = HIGH voltage level; L = LOW voltage level; X = Don't care; Z = high-impedance OFF-state; = LOW to HIGH level transition. Inputs OE H L L L L L L
[1] [2]
Outputs LE X L L H H H H CP X X X H L An X L H L H X X Yn Z L H L H Y0[1] Y0[2]
Output level before the indicated steady-state input conditions were established, provided that CP is HIGH before LE goes LOW. Output level before the indicated steady-state input conditions were established.
74ALVC162334A_3
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Product data sheet
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74ALVC162334A
16-bit registered driver (3-state)
8. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO ICC IGND Tstg Ptot/pack Parameter supply voltage input clamping current input voltage output clamping current output voltage VO = 0 V to VCC supply current ground current storage temperature total power dissipation per package for temperature range -40 C to +125 C; above +55 C derate linearly with 8 mW/K VO > VCC or VO < 0 V
[1]
Conditions VI < 0 V
[1]
Min -0.5 -0.5 -0.5 -65 -
Max +4.6 -50 +4.6 50 VCC + 0.5 50 100 100 +150 600
Unit V mA V mA V mA mA mA C mW
IO(sink/source) output sink or source current
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
9. Recommended operating conditions
Table 6. Symbol VCC Operating conditions Parameter supply voltage Conditions 2.5 V range for maximum speed performance at 30 pF output load 3.3 V range for maximum speed performance at 50 pF output load for low-voltage applications VI VO Tamb tr tf input voltage output voltage ambient temperature rise time fall time operating in free-air VCC = 2.3 V to 3.0 V VCC = 3.0 V to 3.6 V VCC = 2.3 V to 3.0 V VCC = 3.0 V to 3.6 V Min 2.3 3.0 1.2 0 0 -40 0 0 0 0 Typ Max 2.7 3.6 3.6 VCC VCC +85 20 10 20 10 Unit V V V V V C ns/V ns/V ns/V ns/V
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Product data sheet
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74ALVC162334A
16-bit registered driver (3-state)
10. Static characteristics
Table 7. Static characteristics Tamb = -40 C to +85 C; over recommended operating conditions; voltages are referenced to GND (ground = 0 V); unless otherwise specified. Symbol VIH VIL VOH Parameter HIGH-level input voltage LOW-level input voltage Conditions VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V HIGH-level output voltage VI = VIH or VIL VCC = 2.3 V to 3.6 V; IO = -100 A VCC = 2.3 V; IO = -4 mA VCC = 2.3 V; IO = -6 mA VCC = 2.7 V; IO = -4 mA VCC = 2.7 V; IO = -8 mA VCC = 3.0 V; IO = -6 mA VCC = 3.0 V; IO = -12 mA VOL LOW-level output voltage VI = VIH or VIL VCC = 2.3 V to 3.6 V; IO = 100 A VCC = 2.3 V; IO = 4 mA VCC = 2.3 V; IO = 6 mA VCC = 2.7 V; IO = 4 mA VCC = 2.7 V; IO = 8 mA VCC = 3.0 V; IO = 6 mA VCC = 3.0 V; IO = 12 mA ILI IOZ ICC ICC Ci Cio CPD input leakage current off-state output current supply current additional supply current input capacitance input/output capacitance power dissipation capacitance per buffer; VI = GND to VCC transparent mode; output enabled transparent mode; output disabled clocked mode; output enabled clocked mode; output disabled
[1] [2] All typical values are at Tamb = 25 C. CPD is used to determine the dynamic power dissipation (PD) in W. PD = CPD x VCC2 x fi + (CL x VCC2 x fo), where: fi = input frequency in MHz;
(c) NXP B.V. 2006. All rights reserved.
Min 1.7 2.0 VCC - 0.2 VCC - 0.4 VCC - 0.6 VCC - 0.5 VCC - 0.7 VCC - 0.6 VCC - 1.0 [2]
Typ[1] 1.2 1.5 1.2 1.5 VCC VCC - 0.11 VCC - 0.17 VCC - 0.09 VCC - 0.19 VCC - 0.13 VCC - 0.27 GND 0.07 0.11 0.06 0.13 0.09 0.19 0.1 0.1 0.2 150 4.0 8.0 10 3 21 15
Max 0.7 0.8 0.20 0.40 0.55 0.40 0.60 0.55 0.80 5 10 40 750 -
Unit V V V V V V V V V V V V V V V V V V A A A A pF pF pF pF pF pF
VCC = 2.3 V to 3.6 V; VI = VCC or GND 3-state; VCC = 2.3 V to 3.6 V; VI = VIH or VIL; VO = VCC or GND VCC = 2.3 V to 3.6 V; VI = VCC or GND; IO = 0 mA VCC = 2.3 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 mA
-
74ALVC162334A_3
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74ALVC162334A
16-bit registered driver (3-state)
CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of outputs.
11. Dynamic characteristics
Table 8. Dynamic characteristics for VCC = 2.3 V to 2.7 V range VCC = 2.3 V to 2.7 V; GND = 0 V; tr = tf 2.0 ns; CL = 30 pF (see Figure 11). Symbol tPHL Parameter HIGH-to-LOW propagation delay Conditions An to Yn; Figure 5 LE to Yn; Figure 6 CP to Yn; Figure 8 tPLH LOW-to-HIGH propagation delay An to Yn; Figure 5 LE to Yn; Figure 6 CP to Yn; Figure 8 tPZH tPZL tPHZ tPLZ tw tsu th fmax
[1] [2] [3]
Min 1.0 1.3 1.4 1.0 1.3 1.4
[2] [2] [3] [3]
Typ[1] 3.5 3.5 3.7 3.5 3.5 3.7 3.5 3.5 2.8 2.8 1.0 0.7 0.4 0.4 190
Max 5.0 5.0 5.4 5.0 5.0 5.4 5.0 5.0 4.5 4.5 -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
OFF-state to HIGH propagation delay OE to Yn; Figure 10 OFF-state to LOW propagation delay OE to Yn; Figure 10 HIGH to OFF-state propagation delay OE to Yn; Figure 10 LOW to OFF-state propagation delay OE to Yn; Figure 10 pulse width set-up time hold time maximum input clock frequency CP HIGH or LOW; Figure 8 LE HIGH; Figure 6 An to CP; Figure 9 An to LE; Figure 7 An to CP; Figure 9 An to LE; Figure 7 Figure 8
1.4 1.4 1.0 1.0 3.3 3.3 1.0 1.5 0.4 1.4 150
All typical values are at VCC = 2.5 V and Tamb = 25 C. 3-state output enable time. 3-state output disable time.
Table 9. Dynamic characteristics for VCC = 2.7 V VCC = 2.7 V; GND = 0 V; tr = tf 2.5 ns; CL = 50 pF (see Figure 11). Symbol tPHL Parameter HIGH-to-LOW propagation delay Conditions An to Yn; Figure 5 LE to Yn; Figure 6 CP to Yn; Figure 8 tPLH LOW-to-HIGH propagation delay An to Yn; Figure 5 LE to Yn; Figure 6 CP to Yn; Figure 8 tPZH tPZL tPHZ tPLZ
74ALVC162334A_3
Min 1.0 1.3 1.4 1.0 1.3 1.4
[2] [2] [3] [3]
Typ[1] 3.3 3.4 3.8 3.3 3.4 3.8 3.7 3.7 3.5 3.5
Max 4.6 4.8 6.2 4.6 4.8 6.2 6.0 6.0 4.9 4.9
Unit ns ns ns ns ns ns ns ns ns ns
OFF-state to HIGH propagation delay OE to Yn; Figure 10 OFF-state to LOW propagation delay OE to Yn; Figure 10 HIGH to OFF-state propagation delay OE to Yn; Figure 10 LOW to OFF-state propagation delay OE to Yn; Figure 10
1.1 1.1 1.3 1.3
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Product data sheet
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74ALVC162334A
16-bit registered driver (3-state)
Table 9. Dynamic characteristics for VCC = 2.7 V ...continued VCC = 2.7 V; GND = 0 V; tr = tf 2.5 ns; CL = 50 pF (see Figure 11). Symbol tw tsu th fmax
[1] [2] [3]
Parameter pulse width set-up time hold time maximum input clock frequency
Conditions CP HIGH or LOW; Figure 8 LE HIGH; Figure 6 An to CP; Figure 9 An to LE; Figure 7 An to CP; Figure 9 An to LE; Figure 7 Figure 8
Min 3.3 3.3 1.0 1.5 0.6 1.7 150
Typ[1] 1.2 0.6 0.3 0.4 190
Max -
Unit ns ns ns ns ns ns MHz
All typical values are measured at Tamb = 25 C. 3-state output enable time. 3-state output disable time.
Table 10. Dynamic characteristics for VCC = 3.0 V to 3.6 V range VCC = 3.3 V 0.3 V; GND = 0 V; tr = tf 2.5 ns; CL = 50 pF (see Figure 11). Symbol tPHL Parameter HIGH-to-LOW propagation delay Conditions An to Yn; Figure 5 LE to Yn; Figure 6 CP to Yn; Figure 8 tPLH LOW-to-HIGH propagation delay An to Yn; Figure 5 LE to Yn; Figure 6 CP to Yn; Figure 8 tPZH tPZL tPHZ tPLZ tw tsu th fmax
[1] [2] [3]
Min 1.0 1.3 1.4 1.0 1.3 1.4
[2] [2] [3] [3]
Typ[1] 2.8 2.8 3.2 2.8 2.8 3.2 2.4 2.4 2.4 2.4 0.7 0.6 0.3 0.4 240
Max 4.3 4.4 4.9 4.3 4.4 4.9 4.5 4.5 4.8 4.8 -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
OFF-state to HIGH propagation delay OE to Yn; Figure 10 OFF-state to LOW propagation delay OE to Yn; Figure 10 HIGH to OFF-state propagation delay OE to Yn; Figure 10 LOW to OFF-state propagation delay OE to Yn; Figure 10 pulse width set-up time hold time maximum input clock frequency CP HIGH or LOW; Figure 8 LE HIGH; Figure 6 An to CP; Figure 9 An to LE; Figure 7 An to CP; Figure 9 An to LE; Figure 7 Figure 8
1.1 1.1 1.3 1.3 3.3 3.3 1.0 1.5 0.9 1.4 150
All typical values are measured at VCC = 3.3 V, Tamb = 25 C. 3-state output enable time. 3-state output disable time.
74ALVC162334A_3
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Product data sheet
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74ALVC162334A
16-bit registered driver (3-state)
11.1 AC waveforms
VCC = 3.0 V to 3.6 V and VCC = 2.7 V range: VM = 1.5 V; VX = VOL + 0.3 V; VY = VOH - 0.3 V; VI = 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load. VCC = 2.3 V to 2.7 V and VCC < 2.3 V range: VM = 0.5 V; VX = VOL + 0.15 V; VY = VOH - 0.15 V; VI = VCC. VOL and VOH are the typical output voltage drop that occur with the output load.
VI An input VM GND tPHL Yn output VM VOL 002aac726 tPLH VOH Yn output LE input VM tw tPHL VM VM tPLH
VI GND VOH VOL 002aac727
Fig 5. Input (An) to output (Yn) propagation delay
Fig 6. LE input pulse width, LE input to Yn output propagation delays
1 / fmax CP input VM tw tPHL Yn output VM VOL 002aac729 VM GND tPLH VOH
An input
VI VM th tsu tsu VM VM GND
002aac728
VI
VM th GND VI
LE input
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 7. Data set-up and hold times, An input to LE input
Fig 8. CP to Yn propagation delays, clock pulse width, and maximum clock frequency
VI OE input VM GND tPLZ output LOW-to-OFF OFF-to-LOW tPHZ output HIGH-to-OFF OFF-to-HIGH outputs enabled VY VX tPZH VOH VM GND outputs disabled outputs enabled
002aac731
CP input
VI VM tsu th tsu th GND VI GND VOH VOL 002aac730
tPZL VCC VM VOL
An input
Yn output
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 9. Data set-up and hold times, An input to CP input
Fig 10. 3-state enable and disable times
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Product data sheet
Rev. 03 -- 13 December 2006
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NXP Semiconductors
74ALVC162334A
16-bit registered driver (3-state)
12. Test information
S1
VCC PULSE GENERATOR VI DUT
RT CL
VO
RL 500
2 x VCC open GND
RL 500
002aac732
Test data are given in Table 11. RL = load resistance. CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to Zo of pulse generators.
Fig 11. Test circuitry for switching times Table 11. Test data Load tr, tf 2.0 ns 2.5 ns 2.5 ns CL 30 pF 50 pF 50 pF RL 500 500 500 Switch S1 tPLH, tPHL open open open tPZH, tPHZ GND (0 V) GND (0 V) GND (0 V) tPZL, tPLZ 2 x VCC 2 x VCC 2 x VCC
Supply voltage Input VCC VI 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V VCC 2.7 V 2.7 V
74ALVC162334A_3
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Product data sheet
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74ALVC162334A
16-bit registered driver (3-state)
13. Package outline
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
D
E
A X
c y HE vMA
Z
48
25
Q A2 A1 pin 1 index Lp L (A 3) A
1
e bp
24
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 12.6 12.4 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.8 0.4 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 12. Package outline SOT362-1 (TSSOP48)
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Product data sheet
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74ALVC162334A
16-bit registered driver (3-state)
14. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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Product data sheet
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74ALVC162334A
16-bit registered driver (3-state)
14.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 13) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13
Table 12. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 13. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 13.
74ALVC162334A_3
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Product data sheet
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74ALVC162334A
16-bit registered driver (3-state)
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 13. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
15. Abbreviations
Table 14. Acronym CMOS TTL Abbreviations Description Complementary Metal Oxide Semiconductor Transistor-Transistor Logic
16. Revision history
Table 15. Revision history Release date 20061213 Data sheet status Product data sheet Change notice Supersedes 74ALVC162334A_2 Document ID 74ALVC162334A_3 Modifications:
* * * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 1 "General description", 1st paragraph, 2nd sentence: changed "OE" to "OE" Table 2 "Ordering information": changed (SOT364-1; TSSOP56) package to (SOT362-1; TSSOP48) package Table 3 "Pin description" corrected: - changed "Y1 to Y18" to (Y1 to Y16, noted separately) - GND pins: added pins 4 and 39 - VCC pins changed from "7, 22, 35, 50" to "7, 18, 31, 42" - changed "A1 to A18" to (A1 to A16, noted separately)
*
74ALVC162334A_3
Figure 1 "Logic symbol (IEEE/IEC)": corrected pin number for Y15 from "21" to "22"
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74ALVC162334A
16-bit registered driver (3-state)
Table 15.
Revision history ...continued Release date Data sheet status Change notice Supersedes
Document ID Modifications: (continued)
* *
Figure 1 "Logic symbol (IEEE/IEC)": corrected pin number for Y15 from "21" to "22" Figure 2 "Logic diagram": - changed signal "A0" to "A1" - changed signal "Y0" to "Y1" - changed "to the 17 other channels" to "to the 15 other channels"
*
Table 5 "Limiting values" (title changed from "Absolute maximum ratings"): - parameter definition of IIK changed from "DC input diode current" to "input clamping current" - parameter definition of IOK changed from "DC output diode current" to "output clamping current" - symbol "IO" (DC output source or sink current) changed to "IO(sink/source)" (output sink or source current) - removed Ptot/pack information for SSOP package
*
Table 7 "Static characteristics" (title changed from "DC electrical characteristics"): - changed symbol "II" to "ILI" - parameter definition of IOZ changed from "3-State output OFF-state current" to "OFF-state output current" (moved "3-state" to Conditions column) - parameter definition of ICC changed from "quiescent supply current" to "supply current" - parameter definition of ICC changed from "additional quiescent supply current" to "additional supply current" - added Ci, Cio, and CPD parameters
* *
Section 11 "Dynamic characteristics": table "AC characteristics for VCC = 3.0 V to 3.6 V range and VCC = 2.7 V" separated into 2 tables Section 11.1 "AC waveforms": - 1st paragraph, 2nd line: changed "VM = 1.5 VCC" to "VM = 1.5 V" - removed statement "VM = 0.5VCC at VCC = 2.3 V to 2.7 V." from Figure 5, Figure 6, Figure 7, Figure 8, Figure 9 and Figure 10 as redundant (depends on voltage as stated above these figures)
*
74ALVC162334A_2 (9397 750 07246) 74ALVC162334A_1 (9397 750 06963)
Section 13 "Package outline": replaced SOT364-1 (TSSOP56) package outline drawing with Figure 12 "Package outline SOT362-1 (TSSOP48)" Product specification Product specification 853-2197 23931 853-2197 23314 74ALVC162334A_1 -
20000620 20000314
74ALVC162334A_3
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 -- 13 December 2006
17 of 19
NXP Semiconductors
74ALVC162334A
16-bit registered driver (3-state)
17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
74ALVC162334A_3
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 -- 13 December 2006
18 of 19
NXP Semiconductors
74ALVC162334A
16-bit registered driver (3-state)
19. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 11.1 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 6 Function selection. . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 11 Test information . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Introduction to soldering . . . . . . . . . . . . . . . . . 14 Wave and reflow soldering . . . . . . . . . . . . . . . 14 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 14 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2006.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 December 2006 Document identifier: 74ALVC162334A_3

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